AON_TIMER Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	605.700us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.950s	1.315ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	503.750us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	15.040s	11.098ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.830s	671.130us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.720s	586.497us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	503.750us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	671.130us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.330s	502.896us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.040s	331.461us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.634m	60.713ms	50	50	100.00
V2	jump	aon_timer_jump	1.450s	577.439us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.056m	402.526ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.350s	494.341us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.890s	538.150us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.890s	538.150us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.950s	1.315ms	5	5	100.00
		aon_timer_csr_rw	1.370s	503.750us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	671.130us	5	5	100.00
		aon_timer_same_csr_outstanding	6.790s	2.090ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.950s	1.315ms	5	5	100.00
		aon_timer_csr_rw	1.370s	503.750us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	671.130us	5	5	100.00
		aon_timer_same_csr_outstanding	6.790s	2.090ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	6.670s	7.869ms	5	5	100.00
		aon_timer_tl_intg_err	15.070s	8.760ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.070s	8.760ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.945m	93.403ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.91171419286656859080322612672522694021332816350781102204837573385916485714222
Line 575, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31207027111 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 31207027111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.90541809050761851740339181086294187394438084506195934888589513223893921262854
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 958985567 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 958985567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 3 failures.

9.aon_timer_stress_all.39470647798233808799477890434778761685153877643690443648987997810680964833029
Line 261, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 78320227607 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 78320227607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.aon_timer_stress_all.85852138044446916638927940994156738847900083646111427041259610639936981095554
Line 299, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 9251784139 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 9251784139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:753) [aon_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 6.aon_timer_stress_all_with_rand_reset.101672759449948651421446698701555073437543945497506585511919094219725051292373
    Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 507478601 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 507478601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (aon_timer_scoreboard.sv:323) [scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 27.aon_timer_stress_all.78536904764673375785027082078373956115890495929005861485694881421242734548581
    Line 288, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 47534193837 ps: (aon_timer_scoreboard.sv:323) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 47534193837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```