AON_TIMER Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.380s	508.960us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.420s	927.266us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.420s	427.020us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.450s	14.142ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.570s	498.233us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.530s	741.158us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.420s	427.020us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	498.233us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.260s	501.778us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	430.832us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.406m	57.623ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	560.909us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.376m	349.675ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.410s	485.928us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.890s	433.991us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.890s	433.991us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.420s	927.266us	5	5	100.00
		aon_timer_csr_rw	1.420s	427.020us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	498.233us	5	5	100.00
		aon_timer_same_csr_outstanding	7.280s	2.415ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.420s	927.266us	5	5	100.00
		aon_timer_csr_rw	1.420s	427.020us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	498.233us	5	5	100.00
		aon_timer_same_csr_outstanding	7.280s	2.415ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.760s	8.480ms	5	5	100.00
		aon_timer_tl_intg_err	13.640s	8.297ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.640s	8.297ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.931m	91.157ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

7.aon_timer_stress_all_with_rand_reset.104658206971405896224654137116623750819246674624923994009938869813057046163131
Line 640, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 403475956970 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 403475956970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all_with_rand_reset.43520520391346791096573129799152385115640869167728315112433458866839421833586
Line 630, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 106717639079 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 106717639079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 1 failures.

13.aon_timer_stress_all.6431647336721769105091403773019113785408015379632482093918040888382716120341
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 14199308711 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14199308711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---