AON_TIMER Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: `c187a82ee8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	598.275us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.840s	1.074ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.390s	513.238us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	27.150s	13.742ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.990s	612.243us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.700s	612.041us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.390s	513.238us	20	20	100.00
		aon_timer_csr_aliasing	1.990s	612.243us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.140s	396.507us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.080s	334.646us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.342m	55.128ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	557.588us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.579m	326.157ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.290s	500.642us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.770s	519.852us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.770s	519.852us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.840s	1.074ms	5	5	100.00
		aon_timer_csr_rw	1.390s	513.238us	20	20	100.00
		aon_timer_csr_aliasing	1.990s	612.243us	5	5	100.00
		aon_timer_same_csr_outstanding	4.880s	2.829ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.840s	1.074ms	5	5	100.00
		aon_timer_csr_rw	1.390s	513.238us	20	20	100.00
		aon_timer_csr_aliasing	1.990s	612.243us	5	5	100.00
		aon_timer_same_csr_outstanding	4.880s	2.829ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	11.650s	7.372ms	5	5	100.00
		aon_timer_tl_intg_err	13.120s	8.270ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.120s	8.270ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	26.914m	291.662ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.02	99.25	93.67	100.00	--	98.40	99.51	67.30

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all has 3 failures.

6.aon_timer_stress_all.104784751168149807687801133433787155649253576792186885963482602608830387076024
Line 300, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 52991267845 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 52991267845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aon_timer_stress_all.71151233268609240738187459801039254655331067136088634989408091368733758006668
Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 984028890 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 984028890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 6 failures.

8.aon_timer_stress_all_with_rand_reset.64047056086339709468805859075610848847801887523594617335470264012574238670251
Line 487, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 94095827379 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 94095827379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all_with_rand_reset.83343402505762088224838132976429331446219533925599361397578039257603100085730
Line 1144, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 54254836531 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 54254836531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.