AON_TIMER Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.390s	515.965us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.090s	968.752us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	496.449us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.420s	6.831ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.540s	556.986us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	557.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	496.449us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	556.986us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.950s	286.319us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.000s	320.784us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.615m	61.579ms	50	50	100.00
V2	jump	aon_timer_jump	1.440s	550.669us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.078m	492.765ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.340s	504.042us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.750s	550.965us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.750s	550.965us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.090s	968.752us	5	5	100.00
		aon_timer_csr_rw	1.370s	496.449us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	556.986us	5	5	100.00
		aon_timer_same_csr_outstanding	6.180s	2.141ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.090s	968.752us	5	5	100.00
		aon_timer_csr_rw	1.370s	496.449us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	556.986us	5	5	100.00
		aon_timer_same_csr_outstanding	6.180s	2.141ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	12.100s	8.481ms	5	5	100.00
		aon_timer_tl_intg_err	13.490s	7.958ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.490s	7.958ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.976m	113.727ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

4.aon_timer_stress_all_with_rand_reset.107478267436278353647193163717668091407065880331797888524221266151954602364859
Line 721, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 136207565454 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 136207565454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.aon_timer_stress_all_with_rand_reset.12018686316425402337825768743190343044813787310083400710260398734003840015731
Line 816, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45508552499 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 45508552499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 4 failures.

8.aon_timer_stress_all.68806156668103585168253514984300405397073044517239893558446554675823284348311
Line 278, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2973717625 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2973717625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.aon_timer_stress_all.42145697586726735151113913010179854501772057289256105976533088636322763404889
Line 267, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 11785691323 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 11785691323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.