AON_TIMER Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	567.974us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.100s	1.122ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.450s	545.925us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.010s	13.948ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.680s	597.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	488.137us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.450s	545.925us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	597.178us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.090s	441.055us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.270s	471.437us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.522m	59.651ms	50	50	100.00
V2	jump	aon_timer_jump	1.460s	596.132us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.736m	364.728ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.440s	498.504us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.620s	586.028us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.620s	586.028us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.100s	1.122ms	5	5	100.00
		aon_timer_csr_rw	1.450s	545.925us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	597.178us	5	5	100.00
		aon_timer_same_csr_outstanding	6.600s	2.417ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.100s	1.122ms	5	5	100.00
		aon_timer_csr_rw	1.450s	545.925us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	597.178us	5	5	100.00
		aon_timer_same_csr_outstanding	6.600s	2.417ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	6.480s	8.002ms	5	5	100.00
		aon_timer_tl_intg_err	13.290s	9.225ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.290s	9.225ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.663m	500.368ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

4.aon_timer_stress_all_with_rand_reset.78353532255519482595603853232138983299986730061327827220116060365812700034971
Line 1010, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39906204508 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 39906204508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.101968150639011796927201679519249343871244632475579817693331869665771972482405
Line 557, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31279674510 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 31279674510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 2 failures.

26.aon_timer_stress_all.74468662169154548569908926970862746598281654933725767520667182045131833579675
Line 298, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 166766267610 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 166766267610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.aon_timer_stress_all.41692567842519701652704279395164554549271489778741842420989814739647768600048
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 57681182396 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 57681182396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---