AON_TIMER Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.570s	604.581us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.040s	988.300us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	518.249us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.710s	6.987ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.020s	726.816us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	570.948us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	518.249us	20	20	100.00
		aon_timer_csr_aliasing	2.020s	726.816us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.110s	486.379us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	472.675us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.175m	50.868ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	580.563us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.768m	409.363ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.210s	498.366us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.300s	686.562us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.300s	686.562us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.040s	988.300us	5	5	100.00
		aon_timer_csr_rw	1.370s	518.249us	20	20	100.00
		aon_timer_csr_aliasing	2.020s	726.816us	5	5	100.00
		aon_timer_same_csr_outstanding	5.840s	3.215ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.040s	988.300us	5	5	100.00
		aon_timer_csr_rw	1.370s	518.249us	20	20	100.00
		aon_timer_csr_aliasing	2.020s	726.816us	5	5	100.00
		aon_timer_same_csr_outstanding	5.840s	3.215ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	2.390s	4.177ms	5	5	100.00
		aon_timer_tl_intg_err	15.220s	8.234ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.220s	8.234ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.504m	656.081ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

0.aon_timer_stress_all_with_rand_reset.98689281968246465187868355045204156838408075858392048826654541928152892579043
Line 394, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18514543859 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18514543859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aon_timer_stress_all_with_rand_reset.64281213671270401122783542821275420573850579290153363249414297780743982474096
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1246564526 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1246564526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 5 failures.

25.aon_timer_stress_all.48820070177719711781793983225688321124730726829692259806743357442516645495909
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 57137669433 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 57137669433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aon_timer_stress_all.70564017063689591599817685500753561622396962705158397833713449363456367564423
Line 272, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 19162598308 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 19162598308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.