AON_TIMER Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	601.616us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.590s	658.348us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.460s	550.088us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.610s	13.692ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.360s	461.770us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	604.774us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.460s	550.088us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	461.770us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.890s	464.627us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.100s	329.505us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.221m	48.447ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	592.050us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.871m	524.123ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	507.579us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.840s	503.204us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.840s	503.204us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.590s	658.348us	5	5	100.00
		aon_timer_csr_rw	1.460s	550.088us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	461.770us	5	5	100.00
		aon_timer_same_csr_outstanding	6.450s	2.625ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.590s	658.348us	5	5	100.00
		aon_timer_csr_rw	1.460s	550.088us	20	20	100.00
		aon_timer_csr_aliasing	1.360s	461.770us	5	5	100.00
		aon_timer_same_csr_outstanding	6.450s	2.625ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	7.070s	3.963ms	5	5	100.00
		aon_timer_tl_intg_err	14.030s	7.845ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.030s	7.845ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.167m	89.614ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

2.aon_timer_stress_all_with_rand_reset.53747076894962916175861829833052249520023161790073666466184248596788737002295
Line 488, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15822608312 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 15822608312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aon_timer_stress_all_with_rand_reset.23882771315289097746785284989000746139963472079558164568445647096203389267562
Line 395, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12512404606 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 12512404606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 1 failures.

17.aon_timer_stress_all.49248673402349304047432684226507380589549870443998103772283275870110514711462
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 478355557393 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 478355557393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---