AON_TIMER Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	573.944us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.150s	959.630us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.220s	345.183us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.050s	13.918ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.760s	695.108us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	516.873us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.220s	345.183us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	695.108us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.040s	311.994us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.970s	271.504us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.589m	59.603ms	50	50	100.00
V2	jump	aon_timer_jump	1.570s	576.600us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.337m	567.614ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.370s	506.270us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.550s	914.313us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.550s	914.313us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.150s	959.630us	5	5	100.00
		aon_timer_csr_rw	1.220s	345.183us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	695.108us	5	5	100.00
		aon_timer_same_csr_outstanding	6.630s	2.529ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.150s	959.630us	5	5	100.00
		aon_timer_csr_rw	1.220s	345.183us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	695.108us	5	5	100.00
		aon_timer_same_csr_outstanding	6.630s	2.529ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	7.430s	4.330ms	5	5	100.00
		aon_timer_tl_intg_err	15.300s	8.687ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.300s	8.687ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.157m	348.657ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.24852740645097726735896412828435592643304174787477992750001892481919272531652
Line 989, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 69937146427 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 69937146427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.aon_timer_stress_all_with_rand_reset.19092399550720471449151960178339001815892978360657312213068788620402346338109
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 622011816 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 622011816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 2 failures.

29.aon_timer_stress_all.60528529274472900289120196213897023774871247142152354788088662659446725548408
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 32825193665 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 32825193665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.aon_timer_stress_all.12482283643171922903457945167480024204731307599752556313475994672029148836242
Line 296, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 37046012368 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37046012368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:282) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 34.aon_timer_stress_all.88357172875346254941053814629434645541104522787882454579169033677004322149455
    Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 58900364385 ps: (aon_timer_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 58900364385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```