AON_TIMER Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.420s	487.490us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.040s	975.888us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.420s	518.397us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.090s	7.033ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.650s	672.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.460s	505.894us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.420s	518.397us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	672.011us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.990s	297.092us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.230s	409.789us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.587m	59.971ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	589.176us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.361m	370.188ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.340s	506.237us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.290s	533.120us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.290s	533.120us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.040s	975.888us	5	5	100.00
		aon_timer_csr_rw	1.420s	518.397us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	672.011us	5	5	100.00
		aon_timer_same_csr_outstanding	6.060s	2.553ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.040s	975.888us	5	5	100.00
		aon_timer_csr_rw	1.420s	518.397us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	672.011us	5	5	100.00
		aon_timer_same_csr_outstanding	6.060s	2.553ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	8.290s	4.477ms	5	5	100.00
		aon_timer_tl_intg_err	14.320s	8.500ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.320s	8.500ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.999m	88.764ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

1.aon_timer_stress_all_with_rand_reset.71361995048748604279506836932189611318058419782130796291621295387480221117992
Line 644, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14975876056 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14975876056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.74405553681147454000628974545926292461264389613657396131386721400808532849527
Line 1705, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 299316106389 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 299316106389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 2 failures.

6.aon_timer_stress_all.64449398046721044335405739498876095305498107189804846779195428394009693283122
Line 316, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 4971995062 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4971995062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all.14124494975620500779542610974182356574950317232233975108908588142278484077774
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 182665756832 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 182665756832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---