AON_TIMER Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.390s	544.488us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.260s	1.017ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.250s	443.807us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	27.380s	13.936ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.570s	513.449us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.460s	567.380us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.250s	443.807us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	513.449us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.130s	407.084us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.040s	380.278us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.394m	56.200ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	554.810us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.895m	297.664ms	43	50	86.00
V2	intr_test	aon_timer_intr_test	1.360s	517.197us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.930s	396.494us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.930s	396.494us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.260s	1.017ms	5	5	100.00
		aon_timer_csr_rw	1.250s	443.807us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	513.449us	5	5	100.00
		aon_timer_same_csr_outstanding	4.230s	2.839ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.260s	1.017ms	5	5	100.00
		aon_timer_csr_rw	1.250s	443.807us	20	20	100.00
		aon_timer_csr_aliasing	1.570s	513.449us	5	5	100.00
		aon_timer_same_csr_outstanding	4.230s	2.839ms	20	20	100.00
V2		TOTAL			233	240	97.08
V2S	tl_intg_err	aon_timer_sec_cm	11.960s	7.680ms	5	5	100.00
		aon_timer_tl_intg_err	14.020s	8.272ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.020s	8.272ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.441m	164.538ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			413	430	96.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 17 failures:

Test aon_timer_stress_all has 7 failures.

3.aon_timer_stress_all.108716541944359415265268462911230937704749971191048773128520388504996121474893
Line 290, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 159106340852 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 159106340852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aon_timer_stress_all.59696603284350087996252373137967041639340366842960093982064153342747427652660
Line 266, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1969520329 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1969520329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all_with_rand_reset has 10 failures.

8.aon_timer_stress_all_with_rand_reset.100214529478844306092013649437432680019097630407853301064256920733173034305147
Line 528, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 54175998271 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 54175998271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aon_timer_stress_all_with_rand_reset.42382348826338689217130766437679615966832461598313420872506333733068146277507
Line 351, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8612136595 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 8612136595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.