AON_TIMER Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: `eb776817a5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	501.925us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.400s	1.173ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.390s	525.088us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	17.150s	12.334ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.830s	693.340us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.500s	558.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.390s	525.088us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	693.340us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.240s	432.819us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	418.360us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.347m	47.776ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	593.731us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.316m	406.435ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.300s	489.699us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.770s	433.621us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.770s	433.621us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.400s	1.173ms	5	5	100.00
		aon_timer_csr_rw	1.390s	525.088us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	693.340us	5	5	100.00
		aon_timer_same_csr_outstanding	4.230s	1.122ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.400s	1.173ms	5	5	100.00
		aon_timer_csr_rw	1.390s	525.088us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	693.340us	5	5	100.00
		aon_timer_same_csr_outstanding	4.230s	1.122ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	7.390s	8.065ms	5	5	100.00
		aon_timer_tl_intg_err	14.290s	8.717ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.290s	8.717ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.592m	833.737ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

3.aon_timer_stress_all_with_rand_reset.32028185979693580982797460407385278556832162026984623817585345881615620713149
Line 279, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1257566511 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1257566511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.28526285787814505923560711542019615202681988779510330392648734075090180476577
Line 778, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 294365616846 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 294365616846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 4 failures.

3.aon_timer_stress_all.82488240664070762567590806304097667039359531845779586172283370066799926352632
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 31737882014 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 31737882014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all.30760490227713427771792240476499639937345143080425323751147609235952817474566
Line 279, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 28073980356 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 28073980356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.