AON_TIMER Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.420s	552.981us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.190s	1.033ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	503.150us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.950s	13.355ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.130s	520.188us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.550s	583.784us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	503.150us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	520.188us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.720s	297.601us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.070s	367.659us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.454m	55.011ms	50	50	100.00
V2	jump	aon_timer_jump	1.530s	566.457us	50	50	100.00
V2	stress_all	aon_timer_stress_all	15.190m	735.368ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.260s	450.240us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.880s	333.907us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.880s	333.907us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.190s	1.033ms	5	5	100.00
		aon_timer_csr_rw	1.350s	503.150us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	520.188us	5	5	100.00
		aon_timer_same_csr_outstanding	8.090s	2.733ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.190s	1.033ms	5	5	100.00
		aon_timer_csr_rw	1.350s	503.150us	20	20	100.00
		aon_timer_csr_aliasing	1.130s	520.188us	5	5	100.00
		aon_timer_same_csr_outstanding	8.090s	2.733ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	12.300s	7.416ms	5	5	100.00
		aon_timer_tl_intg_err	13.940s	8.294ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.940s	8.294ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.615m	563.394ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all has 2 failures.

4.aon_timer_stress_all.80970105132294824464766419070090955743361577172473802540854291411872187276948
Line 258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 107178402745 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 107178402745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.aon_timer_stress_all.16824414330748620805868192652648886496158548598130506580418522569529569411708
Line 264, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1658179560 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1658179560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 8 failures.

6.aon_timer_stress_all_with_rand_reset.98092021139868045640904688924389976639967624267597115027834038044528473485985
Line 1206, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 99251236054 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 99251236054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all_with_rand_reset.66086040462310049290217596782850983371345207878178829938887617027659313079482
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 743609776 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 743609776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.