AON_TIMER Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	591.489us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	0.950s	1.177ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.210s	413.367us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	28.760s	13.876ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.650s	588.005us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.580s	526.686us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.210s	413.367us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	588.005us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.890s	458.022us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.100s	369.837us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.502m	61.343ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	588.670us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.055m	339.875ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.360s	482.940us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.250s	388.961us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.250s	388.961us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	0.950s	1.177ms	5	5	100.00
		aon_timer_csr_rw	1.210s	413.367us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	588.005us	5	5	100.00
		aon_timer_same_csr_outstanding	5.550s	1.820ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	0.950s	1.177ms	5	5	100.00
		aon_timer_csr_rw	1.210s	413.367us	20	20	100.00
		aon_timer_csr_aliasing	1.650s	588.005us	5	5	100.00
		aon_timer_same_csr_outstanding	5.550s	1.820ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	4.370s	4.316ms	5	5	100.00
		aon_timer_tl_intg_err	15.010s	8.377ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.010s	8.377ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	13.826m	302.828ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.98	99.25	93.67	100.00	--	98.40	99.51	67.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

1.aon_timer_stress_all_with_rand_reset.50740726664196859287597870817128336470234288238620602223242097566080287000164
Line 465, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20417123645 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 20417123645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aon_timer_stress_all_with_rand_reset.44015807530612974281876223574398745746832036494394940275338004364923153915981
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1967898542 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1967898542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 2 failures.

36.aon_timer_stress_all.24845840537204682161368260446093525263233869590780889591407771767348262853345
Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/36.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 575696486 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 575696486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aon_timer_stress_all.22725222346350631613806303304426934333085109963901818200019570069284588356978
Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 933336622 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 933336622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---