AON_TIMER Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.560s	555.962us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.270s	1.157ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	509.329us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	16.670s	13.750ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.330s	523.344us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.530s	556.166us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	509.329us	20	20	100.00
		aon_timer_csr_aliasing	1.330s	523.344us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.110s	508.419us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.140s	391.144us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.584m	61.518ms	50	50	100.00
V2	jump	aon_timer_jump	1.590s	535.126us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.096m	883.150ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.310s	432.935us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.800s	497.615us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.800s	497.615us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.270s	1.157ms	5	5	100.00
		aon_timer_csr_rw	1.300s	509.329us	20	20	100.00
		aon_timer_csr_aliasing	1.330s	523.344us	5	5	100.00
		aon_timer_same_csr_outstanding	6.170s	2.829ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.270s	1.157ms	5	5	100.00
		aon_timer_csr_rw	1.300s	509.329us	20	20	100.00
		aon_timer_csr_aliasing	1.330s	523.344us	5	5	100.00
		aon_timer_same_csr_outstanding	6.170s	2.829ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	13.620s	7.962ms	5	5	100.00
		aon_timer_tl_intg_err	15.150s	8.418ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.150s	8.418ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.139m	2.476s	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.13	99.33	93.67	100.00	--	98.40	99.51	49.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

5.aon_timer_stress_all_with_rand_reset.97760192362465800292017382163544195642602638138115988713352318940431411765125
Line 1526, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 205117715168 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 205117715168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aon_timer_stress_all_with_rand_reset.80253823198820409789920181562415076744790054546732285238841192898150105526939
Line 632, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18582322306 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18582322306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 2 failures.

12.aon_timer_stress_all.73946549189535596486522766068202787769342983745316681699120139283548869537928
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 9780234210 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 9780234210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.96554347579661706767992682337714058238503099951311789329763269614661937038908
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2711738672 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2711738672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---