AON_TIMER Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.640s	585.124us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.300s	1.203ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.400s	519.198us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.910s	8.451ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.720s	681.929us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.690s	583.215us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.400s	519.198us	20	20	100.00
		aon_timer_csr_aliasing	1.720s	681.929us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.780s	270.067us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.250s	489.969us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.446m	51.227ms	50	50	100.00
V2	jump	aon_timer_jump	1.450s	585.800us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.488m	485.488ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.360s	441.628us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.500s	869.956us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.500s	869.956us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.300s	1.203ms	5	5	100.00
		aon_timer_csr_rw	1.400s	519.198us	20	20	100.00
		aon_timer_csr_aliasing	1.720s	681.929us	5	5	100.00
		aon_timer_same_csr_outstanding	7.680s	2.259ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.300s	1.203ms	5	5	100.00
		aon_timer_csr_rw	1.400s	519.198us	20	20	100.00
		aon_timer_csr_aliasing	1.720s	681.929us	5	5	100.00
		aon_timer_same_csr_outstanding	7.680s	2.259ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	7.530s	4.271ms	5	5	100.00
		aon_timer_tl_intg_err	14.060s	8.989ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.060s	8.989ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.512m	237.518ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.06	99.33	93.67	100.00	--	98.40	99.51	49.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

6.aon_timer_stress_all_with_rand_reset.22890032459669983418482467572366761514464005608092862162228031433407626954329
Line 370, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16463032219 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16463032219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aon_timer_stress_all_with_rand_reset.20064302769049560203903167179483981005898215719187057117830481418156529043919
Line 439, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 32752570295 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 32752570295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 2 failures.

6.aon_timer_stress_all.50154381837599948372376537819801924323022094957647495455896673709307532478330
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 26032305908 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 26032305908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aon_timer_stress_all.7529727547264198121585331223238008448848788638760618579579774211987830642906
Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 363258153164 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 363258153164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:300) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 17.aon_timer_stress_all_with_rand_reset.87353505652708244579722772060672168100058311818923027502883929945694783708061
    Line 459, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11415992855 ps: (aon_timer_scoreboard.sv:300) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 11415992855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```