AON_TIMER Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	565.291us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.440s	1.142ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.440s	531.118us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.940s	7.337ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.580s	500.504us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	551.247us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.440s	531.118us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	500.504us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.260s	512.883us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.290s	493.780us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.554m	54.340ms	50	50	100.00
V2	jump	aon_timer_jump	1.620s	612.144us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.102m	465.183ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.360s	489.287us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.900s	410.631us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.900s	410.631us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.440s	1.142ms	5	5	100.00
		aon_timer_csr_rw	1.440s	531.118us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	500.504us	5	5	100.00
		aon_timer_same_csr_outstanding	6.350s	2.108ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.440s	1.142ms	5	5	100.00
		aon_timer_csr_rw	1.440s	531.118us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	500.504us	5	5	100.00
		aon_timer_same_csr_outstanding	6.350s	2.108ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	9.680s	7.903ms	5	5	100.00
		aon_timer_tl_intg_err	14.940s	8.326ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.940s	8.326ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.660m	313.459ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.21	99.33	93.67	100.00	--	98.40	99.51	50.34

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all has 2 failures.

26.aon_timer_stress_all.34954323185786214473770458363249231850789746876485760482803514810160040829942
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 528911235 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 528911235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aon_timer_stress_all.28406547859486751534848900109156125492085541514150404418921377677677288070789
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 888567326 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 888567326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 5 failures.

33.aon_timer_stress_all_with_rand_reset.955490148236417524272644712197604094506127479437487264448101470559666675336
Line 272, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1151550392 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1151550392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.aon_timer_stress_all_with_rand_reset.72050917516429210501013250416012906078311498673020103744111466233124974969387
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 404251038 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 404251038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.