01a208901a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.410s | 514.970us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.010s | 917.975us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.460s | 545.091us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 8.740s | 7.103ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.530s | 491.656us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.410s | 513.866us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.460s | 545.091us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.530s | 491.656us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.240s | 474.882us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.060s | 355.930us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.701m | 61.487ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.470s | 501.011us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 17.811m | 697.461ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.360s | 490.928us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.170s | 522.989us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.170s | 522.989us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.010s | 917.975us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.460s | 545.091us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.530s | 491.656us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 6.530s | 2.431ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.010s | 917.975us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.460s | 545.091us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.530s | 491.656us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 6.530s | 2.431ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 12.900s | 7.755ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 14.230s | 8.154ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 14.230s | 8.154ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 16.394m | 564.081ms | 47 | 50 | 94.00 |
| V3 | TOTAL | 47 | 50 | 94.00 | |||
| TOTAL | 427 | 430 | 99.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.75 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 47.60 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 3 failures:
7.aon_timer_stress_all_with_rand_reset.108816920320204085005463886829219522144265005604170809796737534448426891078130
Line 854, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 355221982671 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 355221982671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.aon_timer_stress_all_with_rand_reset.48395302229366887062245467506271677234213825083884117037500314270431432271656
Line 950, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36175060831 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 36175060831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.