AON_TIMER Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.390s	518.713us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.960s	924.860us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.180s	416.350us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.310s	10.228ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.710s	479.850us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.530s	504.571us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.180s	416.350us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	479.850us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.310s	478.532us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.070s	432.601us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.377m	56.967ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	613.337us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.856m	398.052ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.380s	504.307us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.980s	470.114us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.980s	470.114us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.960s	924.860us	5	5	100.00
		aon_timer_csr_rw	1.180s	416.350us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	479.850us	5	5	100.00
		aon_timer_same_csr_outstanding	8.230s	2.739ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.960s	924.860us	5	5	100.00
		aon_timer_csr_rw	1.180s	416.350us	20	20	100.00
		aon_timer_csr_aliasing	1.710s	479.850us	5	5	100.00
		aon_timer_same_csr_outstanding	8.230s	2.739ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	12.420s	7.356ms	5	5	100.00
		aon_timer_tl_intg_err	14.110s	8.031ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.110s	8.031ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.420m	116.367ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.68	99.33	93.67	100.00	--	98.40	99.51	47.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.19823018870138627172905247499391255792648947773559885769556612454123233454313
Line 814, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 230389316806 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 230389316806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.44811726595719333662108633256431552720002376162421781457507018380614675192285
Line 947, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 202969755746 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 202969755746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 4 failures.

30.aon_timer_stress_all.4581598112322391599104034269399022372767516011542176558136890301557565051398
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 79480244343 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 79480244343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aon_timer_stress_all.60797606175796639756931972270201344701520218202980629994219090702394336956153
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 96470267237 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 96470267237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.