AON_TIMER Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.610s	585.295us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.570s	710.870us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.400s	453.845us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.030s	13.792ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.490s	501.917us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.610s	585.667us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.400s	453.845us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	501.917us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.320s	507.318us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.080s	339.460us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.413m	51.731ms	50	50	100.00
V2	jump	aon_timer_jump	1.580s	565.839us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.841m	455.965ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.350s	516.240us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.850s	544.962us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.850s	544.962us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.570s	710.870us	5	5	100.00
		aon_timer_csr_rw	1.400s	453.845us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	501.917us	5	5	100.00
		aon_timer_same_csr_outstanding	7.200s	2.459ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.570s	710.870us	5	5	100.00
		aon_timer_csr_rw	1.400s	453.845us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	501.917us	5	5	100.00
		aon_timer_same_csr_outstanding	7.200s	2.459ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	12.390s	7.509ms	5	5	100.00
		aon_timer_tl_intg_err	13.960s	7.996ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.960s	7.996ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.412m	273.663ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.04	99.33	93.67	100.00	--	98.40	99.51	49.35

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

8.aon_timer_stress_all_with_rand_reset.80389645676255575224004402269723313987802537724238361189981736770909373347704
Line 1067, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 90022225447 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 90022225447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all_with_rand_reset.69255882631623921840450831314837254567226549831635934601793797251641868095341
Line 516, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 64507865837 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 64507865837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 4 failures.

15.aon_timer_stress_all.53412090651056120392645125903788311094246586357629161215686437145915172338966
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 37563149753 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37563149753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.aon_timer_stress_all.25203553657084413609879281954482866469505406910917201730420630514652107665954
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 46661464808 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 46661464808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.