AON_TIMER Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	517.882us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.040s	1.049ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.500s	545.858us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.100s	13.982ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.760s	644.351us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	574.076us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.500s	545.858us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	644.351us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.010s	322.824us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.090s	406.008us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.316m	50.490ms	50	50	100.00
V2	jump	aon_timer_jump	1.600s	628.615us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.122m	383.687ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.340s	499.681us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.810s	626.777us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.810s	626.777us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.040s	1.049ms	5	5	100.00
		aon_timer_csr_rw	1.500s	545.858us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	644.351us	5	5	100.00
		aon_timer_same_csr_outstanding	5.050s	1.343ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.040s	1.049ms	5	5	100.00
		aon_timer_csr_rw	1.500s	545.858us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	644.351us	5	5	100.00
		aon_timer_same_csr_outstanding	5.050s	1.343ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	11.840s	7.880ms	5	5	100.00
		aon_timer_tl_intg_err	11.520s	8.097ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	11.520s	8.097ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.533m	756.338ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.41	99.33	93.67	100.00	--	98.40	99.51	51.54

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all has 2 failures.

14.aon_timer_stress_all.41963204264861112422774989714156380461346919289420868057662518246229034851678
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 132448408846 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 132448408846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aon_timer_stress_all.68237947056637322296055734674970099142854546506318850202248634328683464013978
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 222485208095 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 222485208095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 4 failures.

16.aon_timer_stress_all_with_rand_reset.11754677950775293221463215983235071725684950651098454969510521122893909520413
Line 544, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 169527181345 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 169527181345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.aon_timer_stress_all_with_rand_reset.79173269801909170224909932536059480849881947453897652685030962875920056786652
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 849219151 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 849219151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.