AON_TIMER Simulation Results

Saturday June 08 2024 00:41:57 UTC

GitHub Revision: `302b24f3c6`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32491226968592963393132943636196950930602503490106290691157604759716956925599

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	581.706us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.450s	1.245ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	524.854us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	32.420s	11.979ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.590s	603.389us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.610s	577.200us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	524.854us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	603.389us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.060s	383.649us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.210s	411.520us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.274m	48.134ms	50	50	100.00
V2	jump	aon_timer_jump	1.550s	575.841us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.346m	370.942ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.300s	480.584us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.470s	567.943us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.470s	567.943us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.450s	1.245ms	5	5	100.00
		aon_timer_csr_rw	1.360s	524.854us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	603.389us	5	5	100.00
		aon_timer_same_csr_outstanding	6.480s	2.649ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.450s	1.245ms	5	5	100.00
		aon_timer_csr_rw	1.360s	524.854us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	603.389us	5	5	100.00
		aon_timer_same_csr_outstanding	6.480s	2.649ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	7.470s	8.105ms	5	5	100.00
		aon_timer_tl_intg_err	14.120s	8.409ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.120s	8.409ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.009m	103.932ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.23	99.33	93.67	100.00	--	98.40	99.51	50.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

2.aon_timer_stress_all_with_rand_reset.30871281766033245500342362912582710443793252213968845200112227264474338121689
Line 264, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 503058883 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 503058883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.aon_timer_stress_all_with_rand_reset.114629103538933320605857632811124971405397028364241545988514663286782146349032
Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3530012333 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3530012333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 3 failures.

28.aon_timer_stress_all.92187165806848732137519426159747562122050581361184829019268982587870231467622
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 34625982591 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 34625982591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aon_timer_stress_all.78035799626711081315672855628299894801264563900165230259168879398422943366085
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 120313000012 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 120313000012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.