AON_TIMER Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.590s	616.240us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.730s	741.615us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	507.215us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	15.110s	11.423ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.400s	636.859us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.350s	537.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	507.215us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	636.859us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.320s	490.164us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	425.212us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.505m	58.260ms	50	50	100.00
V2	jump	aon_timer_jump	1.500s	566.386us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.962m	361.034ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.190s	410.122us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.510s	471.529us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.510s	471.529us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.730s	741.615us	5	5	100.00
		aon_timer_csr_rw	1.360s	507.215us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	636.859us	5	5	100.00
		aon_timer_same_csr_outstanding	7.770s	3.252ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.730s	741.615us	5	5	100.00
		aon_timer_csr_rw	1.360s	507.215us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	636.859us	5	5	100.00
		aon_timer_same_csr_outstanding	7.770s	3.252ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	6.850s	3.886ms	5	5	100.00
		aon_timer_tl_intg_err	14.670s	8.566ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.670s	8.566ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	12.763m	120.664ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.74	99.33	93.67	100.00	--	98.40	99.51	47.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

0.aon_timer_stress_all_with_rand_reset.98613668541093366468761601701372636839628989110203639433961772707130762514453
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 441204856 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 441204856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aon_timer_stress_all_with_rand_reset.6621571388257542615665294464211847893427397327719007688394739859515205764847
Line 287, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1352131030 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1352131030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 3 failures.

14.aon_timer_stress_all.76579782639095553667380406792536139699325824815585713976826580106088494128390
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 86239836822 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 86239836822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aon_timer_stress_all.83546070497783483547077108815126279702088661873046380667258369827053085000674
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 30285409482 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30285409482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.