AON_TIMER Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.550s	565.158us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.610s	1.189ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	445.754us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	34.850s	13.753ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.490s	562.191us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	563.021us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	445.754us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	562.191us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.960s	318.382us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.330s	486.126us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.399m	56.491ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	576.621us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.410m	376.910ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.430s	515.772us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.640s	359.094us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.640s	359.094us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.610s	1.189ms	5	5	100.00
		aon_timer_csr_rw	1.330s	445.754us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	562.191us	5	5	100.00
		aon_timer_same_csr_outstanding	6.020s	2.776ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.610s	1.189ms	5	5	100.00
		aon_timer_csr_rw	1.330s	445.754us	20	20	100.00
		aon_timer_csr_aliasing	1.490s	562.191us	5	5	100.00
		aon_timer_same_csr_outstanding	6.020s	2.776ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	11.110s	7.507ms	5	5	100.00
		aon_timer_tl_intg_err	14.130s	8.387ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.130s	8.387ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.189m	188.695ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.08	99.33	93.67	100.00	--	98.40	99.51	49.57

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all has 5 failures.

8.aon_timer_stress_all.21988619049384571143926172482829487687658409122566351830931349408626337982569
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 31127637793 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 31127637793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aon_timer_stress_all.13803979085970192914523191614568766515792359922355029730745561731491280839431
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 62941231912 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 62941231912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all_with_rand_reset has 7 failures.

14.aon_timer_stress_all_with_rand_reset.101330197447054412062026799335078339781045647722000966676911193900330788960768
Line 490, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18731527196 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18731527196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all_with_rand_reset.91112172614682620614128381481193500976613169158613512581280461564671041938210
Line 259, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 534735173 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 534735173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.