AON_TIMER Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.540s	587.943us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.830s	890.824us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.530s	526.758us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.870s	14.166ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.230s	673.044us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	583.988us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.530s	526.758us	20	20	100.00
		aon_timer_csr_aliasing	2.230s	673.044us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.060s	353.553us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.300s	519.355us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.544m	60.274ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	574.580us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.768m	837.761ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.360s	491.826us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.900s	442.594us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.900s	442.594us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.830s	890.824us	5	5	100.00
		aon_timer_csr_rw	1.530s	526.758us	20	20	100.00
		aon_timer_csr_aliasing	2.230s	673.044us	5	5	100.00
		aon_timer_same_csr_outstanding	4.010s	1.683ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.830s	890.824us	5	5	100.00
		aon_timer_csr_rw	1.530s	526.758us	20	20	100.00
		aon_timer_csr_aliasing	2.230s	673.044us	5	5	100.00
		aon_timer_same_csr_outstanding	4.010s	1.683ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	7.580s	8.770ms	5	5	100.00
		aon_timer_tl_intg_err	14.230s	8.281ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.230s	8.281ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.110m	230.722ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.02	99.33	93.67	100.00	--	98.40	99.51	49.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all has 2 failures.

3.aon_timer_stress_all.41045776477448618067638822061578322892771761894739438252328918736722439420465
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 35801825895 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 35801825895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all.85775624910489734019068521528348321122618368741490395478059897248224028907740
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 168566144891 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 168566144891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 8 failures.

4.aon_timer_stress_all_with_rand_reset.47257940649119467190506518686021992055882837375260629301574178326875598803686
Line 370, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3789809779 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3789809779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aon_timer_stress_all_with_rand_reset.115327006686692673253913112172623991825136521600840764513288211916381769920710
Line 505, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7757102573 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7757102573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.