548a3880d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.500s | 595.905us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.390s | 1.258ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.390s | 442.796us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 18.150s | 14.052ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.390s | 550.390us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.610s | 1.048ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.390s | 442.796us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.390s | 550.390us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.080s | 461.889us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.240s | 483.400us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.152m | 45.850ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.480s | 577.629us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 14.425m | 737.839ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.320s | 503.143us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.940s | 572.099us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.940s | 572.099us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.390s | 1.258ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.390s | 442.796us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.390s | 550.390us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 5.790s | 2.075ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.390s | 1.258ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.390s | 442.796us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.390s | 550.390us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 5.790s | 2.075ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 14.050s | 8.629ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 13.590s | 8.030ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 13.590s | 8.030ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 22.336m | 605.970ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 424 | 430 | 98.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.85 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 48.20 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:
5.aon_timer_stress_all_with_rand_reset.107975059676455458998769481477731850250615565699081363714202910619083730523050
Line 553, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20372340712 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 20372340712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.aon_timer_stress_all_with_rand_reset.6375642356060181965696587122952016802368584468237977664654516144689927300255
Line 1440, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 84926998828 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 84926998828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.