AON_TIMER Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	575.224us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.680s	819.655us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.340s	542.495us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	25.960s	11.714ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.530s	613.499us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	547.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.340s	542.495us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	613.499us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.120s	391.309us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.250s	509.837us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.371m	59.316ms	50	50	100.00
V2	jump	aon_timer_jump	1.460s	587.221us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.656m	557.114ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.180s	456.938us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.660s	344.872us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.660s	344.872us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.680s	819.655us	5	5	100.00
		aon_timer_csr_rw	1.340s	542.495us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	613.499us	5	5	100.00
		aon_timer_same_csr_outstanding	3.890s	1.087ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.680s	819.655us	5	5	100.00
		aon_timer_csr_rw	1.340s	542.495us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	613.499us	5	5	100.00
		aon_timer_same_csr_outstanding	3.890s	1.087ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	6.770s	4.212ms	5	5	100.00
		aon_timer_tl_intg_err	14.270s	8.598ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.270s	8.598ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.197m	371.141ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.64	99.33	93.67	100.00	--	98.40	99.51	46.94

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

6.aon_timer_stress_all_with_rand_reset.60087212173141621628769746195466925529932077213897133271917505704370880545477
Line 1376, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 304583357658 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 304583357658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.aon_timer_stress_all_with_rand_reset.55262344742531824699318608522874603772783887045771597459841003881251731596426
Line 503, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 70714281061 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 70714281061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 5 failures.

10.aon_timer_stress_all.70224988969310613816486989200739330582550122092559690172322396827867461797878
Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 78530701636 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 78530701636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.aon_timer_stress_all.50797768039884323226975249418132764338471543784329942608198153403997477844991
Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 137312026831 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 137312026831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:300) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 2 failures:
- Test aon_timer_stress_all_with_rand_reset has 2 failures.
  - 34.aon_timer_stress_all_with_rand_reset.48140921377615105434445907037109852431298443830229089760971667677131354688356
    Line 875, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 353822599195 ps: (aon_timer_scoreboard.sv:300) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 353822599195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aon_timer_stress_all_with_rand_reset.115528100547829938128008220447667531346703729936292309969161026796183516132696
    Line 395, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26231229992 ps: (aon_timer_scoreboard.sv:300) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 26231229992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```