AON_TIMER Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: `8fdb25c8d9`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	556.807us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.030s	1.096ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	466.843us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	17.900s	6.998ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.450s	602.295us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	597.822us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	466.843us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	602.295us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.800s	498.716us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.440s	505.224us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.132m	54.655ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	588.624us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.167m	556.469ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.250s	454.816us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.860s	444.103us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.860s	444.103us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.030s	1.096ms	5	5	100.00
		aon_timer_csr_rw	1.350s	466.843us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	602.295us	5	5	100.00
		aon_timer_same_csr_outstanding	6.300s	2.597ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.030s	1.096ms	5	5	100.00
		aon_timer_csr_rw	1.350s	466.843us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	602.295us	5	5	100.00
		aon_timer_same_csr_outstanding	6.300s	2.597ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	12.600s	8.356ms	5	5	100.00
		aon_timer_tl_intg_err	14.340s	8.417ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.340s	8.417ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.198m	116.399ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.08	99.33	93.67	100.00	--	98.40	99.51	49.57

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

2.aon_timer_stress_all_with_rand_reset.28498510308839961004732415624898465422465984909253936620279272729397674444314
Line 268, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 595441569 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 595441569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.103605071644368999830754123808490456368166065577299818105657638706410434614865
Line 377, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10126365604 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 10126365604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 1 failures.

38.aon_timer_stress_all.82337190204605438542501378996856450074448771791974823959657257286988046999579
Line 265, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 42922842997 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 42922842997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:300) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 40.aon_timer_stress_all.37364466318962702170689752717904965565040316025537856251997291934758822711443
    Line 262, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 152060033634 ps: (aon_timer_scoreboard.sv:300) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 152060033634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```