25e609d6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.470s | 575.695us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.450s | 1.186ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.150s | 409.214us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 7.660s | 10.041ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.950s | 629.651us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.300s | 462.551us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.150s | 409.214us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.950s | 629.651us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.910s | 277.129us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.140s | 437.798us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.479m | 55.224ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.520s | 581.587us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 13.646m | 528.467ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.330s | 498.606us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.120s | 545.889us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.120s | 545.889us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.450s | 1.186ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.150s | 409.214us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.950s | 629.651us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.720s | 3.247ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.450s | 1.186ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.150s | 409.214us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.950s | 629.651us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.720s | 3.247ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 14.170s | 8.434ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 14.290s | 8.543ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 14.290s | 8.543ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 19.928m | 449.535ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 423 | 430 | 98.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.49 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 52.07 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 7 failures:
2.aon_timer_stress_all_with_rand_reset.48327455158524788184732005966991061272219339758700390844636394045861710788949
Line 452, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 126256033225 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 126256033225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.aon_timer_stress_all_with_rand_reset.81625738557581939307729376521501678661570797803671445199799447548338032410941
Line 397, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6135503643 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 6135503643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.