AON_TIMER Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.430s	529.191us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.130s	1.305ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.440s	558.235us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.260s	8.925ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.350s	492.209us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.660s	622.074us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.440s	558.235us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	492.209us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.140s	441.122us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.210s	502.245us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.141m	46.724ms	50	50	100.00
V2	jump	aon_timer_jump	1.460s	598.082us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.036m	310.200ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.340s	517.717us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.090s	515.009us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.090s	515.009us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.130s	1.305ms	5	5	100.00
		aon_timer_csr_rw	1.440s	558.235us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	492.209us	5	5	100.00
		aon_timer_same_csr_outstanding	5.510s	2.073ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.130s	1.305ms	5	5	100.00
		aon_timer_csr_rw	1.440s	558.235us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	492.209us	5	5	100.00
		aon_timer_same_csr_outstanding	5.510s	2.073ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	12.050s	7.615ms	5	5	100.00
		aon_timer_tl_intg_err	13.460s	8.129ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.460s	8.129ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.387m	323.314ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.37	99.33	93.67	100.00	--	98.40	99.51	51.29

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

0.aon_timer_stress_all_with_rand_reset.15230308992027974027695117596399486064072303123245062024453178928151654406722
Line 490, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60647543357 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 60647543357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aon_timer_stress_all_with_rand_reset.60157092577620510211020611228221142050370587999844974712742196447383040944963
Line 643, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 34312423014 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 34312423014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 3 failures.

28.aon_timer_stress_all.99935351713241615364310406941953758943500022035343175675625730531922288306833
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 77717945924 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 77717945924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.aon_timer_stress_all.78250579404582729996950326969451554635656170054443522957232160121002139400952
Line 265, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1741488176 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1741488176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.