3fd3528c8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.490s | 554.032us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.460s | 1.338ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.460s | 528.990us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 35.880s | 13.809ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.700s | 659.996us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.540s | 558.218us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.460s | 528.990us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.700s | 659.996us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.090s | 455.289us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.210s | 446.042us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.305m | 50.570ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.430s | 521.299us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 6.260m | 296.579ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.310s | 490.479us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.990s | 476.668us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.990s | 476.668us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.460s | 1.338ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.460s | 528.990us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.700s | 659.996us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.990s | 2.950ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.460s | 1.338ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.460s | 528.990us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.700s | 659.996us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.990s | 2.950ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 12.050s | 7.758ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 13.630s | 9.044ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 13.630s | 9.044ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 21.211m | 121.215ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 426 | 430 | 99.07 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.53 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 52.31 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 4 failures:
8.aon_timer_stress_all_with_rand_reset.59090953840221983450273771864659235824953922742897197946523527918577851393559
Line 1749, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 145846812881 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 145846812881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.aon_timer_stress_all_with_rand_reset.53586951038368473326089328454402509562489319028491023308106870961724090957005
Line 326, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13916356388 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 13916356388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.