be1c4a4f52| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.390s | 601.560us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.740s | 908.252us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.220s | 498.695us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 13.290s | 6.213ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.380s | 457.250us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.500s | 559.597us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.220s | 498.695us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.380s | 457.250us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.080s | 465.270us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.900s | 486.982us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.221m | 52.196ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.600s | 540.045us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 9.476m | 371.737ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.320s | 461.842us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.100s | 434.836us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.100s | 434.836us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.740s | 908.252us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.220s | 498.695us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.380s | 457.250us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.900s | 2.884ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.740s | 908.252us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.220s | 498.695us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.380s | 457.250us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.900s | 2.884ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 11.090s | 7.702ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 14.290s | 8.853ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 14.290s | 8.853ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 18.708m | 301.543ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 426 | 430 | 99.07 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.43 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 51.67 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 4 failures:
11.aon_timer_stress_all_with_rand_reset.111888351207701161075574533784567501904297539483098512434320184324192684519071
Line 266, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 482907757 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 482907757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.aon_timer_stress_all_with_rand_reset.68227318946559000063330337666390191856861521067058684250443868735214241837642
Line 336, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7998338052 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 7998338052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.