AON_TIMER Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.520s	583.452us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.710s	848.143us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.280s	539.939us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.200s	13.950ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.790s	571.448us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.220s	423.365us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.280s	539.939us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	571.448us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.670s	451.803us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.090s	397.868us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.431m	54.602ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	584.412us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.082m	411.774ms	44	50	88.00
V2	intr_test	aon_timer_intr_test	1.290s	488.629us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.020s	519.752us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.020s	519.752us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.710s	848.143us	5	5	100.00
		aon_timer_csr_rw	1.280s	539.939us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	571.448us	5	5	100.00
		aon_timer_same_csr_outstanding	6.540s	2.508ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.710s	848.143us	5	5	100.00
		aon_timer_csr_rw	1.280s	539.939us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	571.448us	5	5	100.00
		aon_timer_same_csr_outstanding	6.540s	2.508ms	20	20	100.00
V2		TOTAL			234	240	97.50
V2S	tl_intg_err	aon_timer_sec_cm	6.780s	4.203ms	5	5	100.00
		aon_timer_tl_intg_err	7.620s	4.269ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	7.620s	4.269ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.104m	360.431ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.31	99.33	93.67	100.00	--	98.40	99.51	50.96

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all has 6 failures.

5.aon_timer_stress_all.13537038106833883984958154947838819559456607578708825303182603093956437774847
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 169222961367 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 169222961367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all.41423478327033109574381611796551560870613777283997537332501154012938501737260
Line 265, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 47271880392 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 47271880392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all_with_rand_reset has 4 failures.

6.aon_timer_stress_all_with_rand_reset.38700820577183851486093266477474423255418715362884928905702475454942353083634
Line 568, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16515711202 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16515711202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.aon_timer_stress_all_with_rand_reset.64455610874830696441937615288285655878666944002324467550950263556493398175974
Line 1226, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 179935137503 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 179935137503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.