AON_TIMER Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	584.576us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.630s	1.313ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.220s	403.631us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.170s	7.633ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.900s	476.637us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.400s	576.601us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.220s	403.631us	20	20	100.00
		aon_timer_csr_aliasing	1.900s	476.637us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.950s	322.800us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.250s	497.842us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.338m	52.537ms	50	50	100.00
V2	jump	aon_timer_jump	1.500s	569.666us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.570m	392.200ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.340s	501.598us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.920s	470.233us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.920s	470.233us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.630s	1.313ms	5	5	100.00
		aon_timer_csr_rw	1.220s	403.631us	20	20	100.00
		aon_timer_csr_aliasing	1.900s	476.637us	5	5	100.00
		aon_timer_same_csr_outstanding	5.550s	2.152ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.630s	1.313ms	5	5	100.00
		aon_timer_csr_rw	1.220s	403.631us	20	20	100.00
		aon_timer_csr_aliasing	1.900s	476.637us	5	5	100.00
		aon_timer_same_csr_outstanding	5.550s	2.152ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	13.020s	8.078ms	5	5	100.00
		aon_timer_tl_intg_err	13.940s	8.264ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.940s	8.264ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	13.331m	174.998ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.34	99.33	93.67	100.00	--	98.40	99.51	51.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all has 3 failures.

0.aon_timer_stress_all.95772960849653409738684071552798993742077500699390744564120983126034559609062
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 80269728250 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 80269728250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all.34789133733285787044795242248693285124677881868742988100087779704646701979705
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 172170479567 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 172170479567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 5 failures.

1.aon_timer_stress_all_with_rand_reset.104246298459323866352293705337778357519476677850856101032165897271090825819186
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7381783342 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7381783342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aon_timer_stress_all_with_rand_reset.78229185089894793181603356071062232670663826625079123476112984724184621153574
Line 780, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33825836791 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 33825836791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.