b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.460s | 550.400us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.930s | 1.060ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.410s | 489.520us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 15.080s | 7.035ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.680s | 617.925us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.500s | 566.217us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.410s | 489.520us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.680s | 617.925us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.960s | 364.843us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.840s | 520.816us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.515m | 58.278ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.400s | 549.235us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 14.964m | 645.028ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.330s | 517.812us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.770s | 584.519us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.770s | 584.519us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.930s | 1.060ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.410s | 489.520us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.680s | 617.925us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.570s | 2.234ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.930s | 1.060ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.410s | 489.520us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.680s | 617.925us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.570s | 2.234ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 7.790s | 4.467ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 14.450s | 8.235ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 14.450s | 8.235ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 17.646m | 400.652ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 423 | 430 | 98.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.21 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 50.34 |
UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 7 failures:
11.aon_timer_stress_all_with_rand_reset.98198890365304453346323819654306759908554232384990865884085969014000989889173
Line 806, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47732608688 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 47732608688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.aon_timer_stress_all_with_rand_reset.86962539180766808677595137903331331169809973537767047439299706313136158523931
Line 730, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 267610045045 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 267610045045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.