AON_TIMER Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.510s	564.060us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.300s	1.040ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	517.587us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.420s	7.522ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.380s	518.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.660s	591.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	517.587us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	518.669us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.120s	445.449us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.980s	336.223us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.422m	56.598ms	50	50	100.00
V2	jump	aon_timer_jump	1.470s	539.053us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.371m	532.574ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.310s	481.962us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.930s	437.669us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.930s	437.669us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.300s	1.040ms	5	5	100.00
		aon_timer_csr_rw	1.360s	517.587us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	518.669us	5	5	100.00
		aon_timer_same_csr_outstanding	4.190s	2.649ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.300s	1.040ms	5	5	100.00
		aon_timer_csr_rw	1.360s	517.587us	20	20	100.00
		aon_timer_csr_aliasing	1.380s	518.669us	5	5	100.00
		aon_timer_same_csr_outstanding	4.190s	2.649ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	12.360s	7.500ms	5	5	100.00
		aon_timer_tl_intg_err	10.800s	7.813ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	10.800s	7.813ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.973m	84.775ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.25	99.33	93.67	100.00	--	98.40	99.51	50.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all has 4 failures.

5.aon_timer_stress_all.91593413485612292699765923024491337821260414588597366664899471765636928646626
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 148634198946 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 148634198946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all.108213110635086369172037141595316454160705565806699139236895958783112039859633
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 130807099297 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 130807099297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 5 failures.

18.aon_timer_stress_all_with_rand_reset.17207553385366261719355680084036689138177132053460008328943122061357403001515
Line 640, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 84315714722 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 84315714722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aon_timer_stress_all_with_rand_reset.71468788426629939559698619088586494799397618734022150377943538191357843270398
Line 471, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17748875034 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 17748875034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.