AON_TIMER Simulation Results

Monday July 01 2024 17:07:21 UTC

GitHub Revision: `eb56ef55d0`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 287373712151371957859909226915296476629077008125381265920192201371239303276

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	597.296us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.690s	1.398ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.230s	490.084us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	49.450s	14.132ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.350s	445.728us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.590s	609.161us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.230s	490.084us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	445.728us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.110s	377.661us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.130s	434.147us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.232m	50.910ms	50	50	100.00
V2	jump	aon_timer_jump	1.460s	573.648us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.952m	589.314ms	44	50	88.00
V2	intr_test	aon_timer_intr_test	1.270s	458.094us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.810s	488.678us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.810s	488.678us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.690s	1.398ms	5	5	100.00
		aon_timer_csr_rw	1.230s	490.084us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	445.728us	5	5	100.00
		aon_timer_same_csr_outstanding	5.680s	2.793ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.690s	1.398ms	5	5	100.00
		aon_timer_csr_rw	1.230s	490.084us	20	20	100.00
		aon_timer_csr_aliasing	1.350s	445.728us	5	5	100.00
		aon_timer_same_csr_outstanding	5.680s	2.793ms	20	20	100.00
V2		TOTAL			234	240	97.50
V2S	tl_intg_err	aon_timer_sec_cm	7.400s	4.547ms	5	5	100.00
		aon_timer_tl_intg_err	12.670s	7.972ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.670s	7.972ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.125m	486.511ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			416	430	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.88	99.33	93.67	100.00	--	98.40	99.51	48.40

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 14 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

1.aon_timer_stress_all_with_rand_reset.106453626630055470546601635370665326520023231589004350265988621025276901662466
Line 1039, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 55038520229 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 55038520229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.67908396657871095762353822866913371858836310834527831183560992054845512773784
Line 816, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 240627719988 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 240627719988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 6 failures.

4.aon_timer_stress_all.33004336912363966163659660825488342752757127785265739474413333456782348613229
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 918786615 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 918786615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aon_timer_stress_all.75184452899838031583958073710318719577611560585302949481066087975614161343709
Line 265, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 50640758725 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 50640758725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.