AON_TIMER Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: `e9ae10fb42`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.420s	574.722us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.110s	1.101ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	469.595us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.190s	14.011ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.100s	647.298us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.480s	567.936us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	469.595us	20	20	100.00
		aon_timer_csr_aliasing	2.100s	647.298us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.970s	289.223us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.200s	447.097us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.452m	58.004ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	573.896us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.406m	570.580ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.360s	518.588us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.460s	359.890us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.460s	359.890us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.110s	1.101ms	5	5	100.00
		aon_timer_csr_rw	1.300s	469.595us	20	20	100.00
		aon_timer_csr_aliasing	2.100s	647.298us	5	5	100.00
		aon_timer_same_csr_outstanding	5.710s	2.308ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.110s	1.101ms	5	5	100.00
		aon_timer_csr_rw	1.300s	469.595us	20	20	100.00
		aon_timer_csr_aliasing	2.100s	647.298us	5	5	100.00
		aon_timer_same_csr_outstanding	5.710s	2.308ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	10.650s	7.810ms	5	5	100.00
		aon_timer_tl_intg_err	13.400s	8.636ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.400s	8.636ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	10.967m	930.270ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.08	99.33	93.67	100.00	--	98.40	99.51	49.59

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:473) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all_with_rand_reset has 9 failures.

6.aon_timer_stress_all_with_rand_reset.97819204416498734334052067930857139340196198346612223324561361106492000259220
Line 452, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30807172280 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30807172280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all_with_rand_reset.29645934051032406671135946183196552964234200916200773294943601943431102442580
Line 696, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37151166966 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37151166966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test aon_timer_stress_all has 3 failures.

17.aon_timer_stress_all.29722342100954216606938263992717915915957698485314262577979283474445154799668
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 991318630 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 991318630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.aon_timer_stress_all.71745579453745045903593286865928254552410636457203143054147635321166625168953
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 113456154994 ps: (cip_base_vseq.sv:473) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 113456154994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.