abd7ce57f2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.410s | 616.940us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.870s | 977.230us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.290s | 403.530us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 22.590s | 13.468ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.360s | 500.265us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.550s | 930.560us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.290s | 403.530us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.360s | 500.265us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.990s | 359.106us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.140s | 426.384us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.300m | 59.129ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.440s | 551.596us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 17.524m | 797.604ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.310s | 511.683us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.650s | 458.144us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.650s | 458.144us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.870s | 977.230us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.290s | 403.530us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.360s | 500.265us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 5.600s | 2.689ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.870s | 977.230us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.290s | 403.530us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.360s | 500.265us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 5.600s | 2.689ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 6.860s | 8.225ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 12.130s | 7.817ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 12.130s | 7.817ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 17.071m | 178.642ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 425 | 430 | 98.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.09 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 49.66 |
UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 5 failures:
10.aon_timer_stress_all_with_rand_reset.43958327793185526499347043964494744532316052553288894869421342861100991778214
Line 275, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1395791441 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1395791441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.aon_timer_stress_all_with_rand_reset.68431925891345771192823329494986215748054914870928238137216659032012724532974
Line 488, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 56659515387 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 56659515387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.