AON_TIMER Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: `e6706fcc7b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.490s	607.954us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.380s	1.309ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	479.633us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.310s	6.483ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.540s	601.518us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	573.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	479.633us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	601.518us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	378.633us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.100s	404.857us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.346m	51.237ms	50	50	100.00
V2	jump	aon_timer_jump	1.470s	567.253us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.756m	773.944ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.200s	491.724us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.760s	872.689us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.760s	872.689us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.380s	1.309ms	5	5	100.00
		aon_timer_csr_rw	1.410s	479.633us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	601.518us	5	5	100.00
		aon_timer_same_csr_outstanding	6.270s	3.017ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.380s	1.309ms	5	5	100.00
		aon_timer_csr_rw	1.410s	479.633us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	601.518us	5	5	100.00
		aon_timer_same_csr_outstanding	6.270s	3.017ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	12.280s	8.143ms	5	5	100.00
		aon_timer_tl_intg_err	12.440s	8.288ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.440s	8.288ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.586m	290.836ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.36	99.33	93.67	100.00	--	98.40	99.51	51.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all has 3 failures.

7.aon_timer_stress_all.30932883534524009916008087561491680345724518775160529588012633247582738425203
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 18631289335 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18631289335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aon_timer_stress_all.64255062658405683317895201836101788589222898809774935512000811300037038664458
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 48946101824 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 48946101824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 6 failures.

11.aon_timer_stress_all_with_rand_reset.43227414121682440342119727987451627060656696899446280071888527218502259720329
Line 743, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23625588198 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 23625588198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all_with_rand_reset.80346061041119147739734929743274652845089974757308063376004814826340267548691
Line 1160, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49620696300 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 49620696300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.