AON_TIMER Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: `3e678c112b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.570s	583.898us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.510s	1.237ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.390s	528.488us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.160s	13.862ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.300s	535.896us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.500s	604.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.390s	528.488us	20	20	100.00
		aon_timer_csr_aliasing	1.300s	535.896us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.150s	403.316us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	514.231us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.093m	48.793ms	50	50	100.00
V2	jump	aon_timer_jump	1.570s	598.092us	50	50	100.00
V2	stress_all	aon_timer_stress_all	15.534m	630.461ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.450s	486.561us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.870s	904.591us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.870s	904.591us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.510s	1.237ms	5	5	100.00
		aon_timer_csr_rw	1.390s	528.488us	20	20	100.00
		aon_timer_csr_aliasing	1.300s	535.896us	5	5	100.00
		aon_timer_same_csr_outstanding	5.270s	2.526ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.510s	1.237ms	5	5	100.00
		aon_timer_csr_rw	1.390s	528.488us	20	20	100.00
		aon_timer_csr_aliasing	1.300s	535.896us	5	5	100.00
		aon_timer_same_csr_outstanding	5.270s	2.526ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	6.020s	4.039ms	5	5	100.00
		aon_timer_tl_intg_err	13.870s	8.501ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.870s	8.501ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.249m	222.372ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			416	430	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.96	99.33	93.67	100.00	--	98.40	99.51	48.84

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 10 failures.

15.aon_timer_stress_all_with_rand_reset.104119389065919467811269220266685559941608773845916876681380462475011407720257
Line 747, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 58753625919 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 58753625919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.53699270628416623055850186148300179963367253690466305469229096147942183039538
Line 1020, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 232997189073 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 232997189073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test aon_timer_stress_all has 3 failures.

15.aon_timer_stress_all.18455160766945833345551573027967191018201906696521227155272126606469489417740
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 103576849019 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 103576849019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aon_timer_stress_all.85163054063975519698836285687225775805420446225012117512369323964851389319360
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 82810840889 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 82810840889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:304) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 23.aon_timer_stress_all_with_rand_reset.76106003888905281378677176111602977271833933343631220267533556811192879511753
    Line 355, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13999800360 ps: (aon_timer_scoreboard.sv:304) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 13999800360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```