AON_TIMER Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: `9edf84e236`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	611.478us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.790s	1.139ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	479.491us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.210s	7.084ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.790s	579.838us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.550s	522.620us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	479.491us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	579.838us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.180s	416.486us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.050s	400.134us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.456m	59.117ms	50	50	100.00
V2	jump	aon_timer_jump	1.560s	606.269us	50	50	100.00
V2	stress_all	aon_timer_stress_all	8.348m	364.562ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.270s	514.528us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.740s	897.290us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.740s	897.290us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.790s	1.139ms	5	5	100.00
		aon_timer_csr_rw	1.360s	479.491us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	579.838us	5	5	100.00
		aon_timer_same_csr_outstanding	3.960s	2.693ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.790s	1.139ms	5	5	100.00
		aon_timer_csr_rw	1.360s	479.491us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	579.838us	5	5	100.00
		aon_timer_same_csr_outstanding	3.960s	2.693ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	6.810s	8.199ms	5	5	100.00
		aon_timer_tl_intg_err	11.490s	8.618ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	11.490s	8.618ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	24.907m	761.157ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.24	99.33	93.67	100.00	--	98.40	99.51	56.53

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

6.aon_timer_stress_all_with_rand_reset.3813376724656234891282166861155797004044253340286460618900571092181344909095
Line 537, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48841294026 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 48841294026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.115095584109363393077506899378177647706749837670028963615075229995050013616996
Line 260, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1042848996 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1042848996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 2 failures.

45.aon_timer_stress_all.109621945796953115941195577355563151807586766277526078810086220979950261282914
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/45.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 149797043593 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 149797043593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aon_timer_stress_all.102674105720989502796812731779077577976657552582713980338159001679470320024400
Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 57354509928 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 57354509928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---