AON_TIMER Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: `c42c47ec2d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	580.624us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.890s	942.470us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	452.445us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.590s	7.372ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.530s	498.758us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.340s	444.874us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	452.445us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	498.758us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.760s	353.171us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.200s	511.290us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.466m	60.996ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	554.584us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.016m	424.870ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.350s	481.123us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.690s	614.494us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.690s	614.494us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.890s	942.470us	5	5	100.00
		aon_timer_csr_rw	1.410s	452.445us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	498.758us	5	5	100.00
		aon_timer_same_csr_outstanding	5.130s	2.138ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.890s	942.470us	5	5	100.00
		aon_timer_csr_rw	1.410s	452.445us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	498.758us	5	5	100.00
		aon_timer_same_csr_outstanding	5.130s	2.138ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	11.730s	7.745ms	5	5	100.00
		aon_timer_tl_intg_err	13.750s	8.488ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.750s	8.488ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	13.905m	101.994ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.28	99.33	93.67	100.00	--	98.40	99.51	50.78

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all has 2 failures.

11.aon_timer_stress_all.96233565898352659283217618422199574566382052568806146528330235877181887282755
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 18152232273 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18152232273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.aon_timer_stress_all.37874941896272220889768910335840267353699609799063630737028521872976524606261
Line 261, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1428907370 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1428907370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 6 failures.

21.aon_timer_stress_all_with_rand_reset.75087491002493562226201159488191758966996657538162693644228681630123594574009
Line 351, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6728450366 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6728450366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.aon_timer_stress_all_with_rand_reset.30061273246410529995634819329322422202115222428821633332091324978577710356032
Line 399, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12664292729 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 12664292729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.