AON_TIMER Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.460s	578.383us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.720s	1.312ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.390s	535.314us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	38.230s	10.203ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.410s	689.447us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.670s	601.816us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.390s	535.314us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	689.447us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	402.876us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.000s	326.699us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.491m	60.282ms	50	50	100.00
V2	jump	aon_timer_jump	1.530s	558.587us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.778m	313.550ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.260s	499.882us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.980s	420.600us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.980s	420.600us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.720s	1.312ms	5	5	100.00
		aon_timer_csr_rw	1.390s	535.314us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	689.447us	5	5	100.00
		aon_timer_same_csr_outstanding	6.040s	2.668ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.720s	1.312ms	5	5	100.00
		aon_timer_csr_rw	1.390s	535.314us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	689.447us	5	5	100.00
		aon_timer_same_csr_outstanding	6.040s	2.668ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	10.360s	8.697ms	5	5	100.00
		aon_timer_tl_intg_err	14.570s	8.614ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.570s	8.614ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.002m	438.362ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.09	99.33	93.67	100.00	--	98.40	99.51	49.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

5.aon_timer_stress_all_with_rand_reset.66046893324354959050427310203324251590967952921457731279908437838692149513491
Line 338, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6461044243 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6461044243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aon_timer_stress_all_with_rand_reset.398698232058145951621714707489395686056592044689636478943995370153727457616
Line 2201, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 438361949647 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 438361949647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 3 failures.

7.aon_timer_stress_all.31099263247721983279561607412716730302640801438624535331172343455469446032844
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 16366593321 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16366593321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all.103419523905922906196813658060195404784575235347470097233442854156409221381989
Line 301, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 357784954474 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 357784954474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.