AON_TIMER Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	609.130us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.410s	1.260ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.340s	498.759us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	25.250s	13.300ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.370s	479.813us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	500.526us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.340s	498.759us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	479.813us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.020s	432.474us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.050s	428.296us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.367m	52.927ms	50	50	100.00
V2	jump	aon_timer_jump	1.400s	525.980us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.096m	541.435ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.300s	504.239us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.890s	966.926us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.890s	966.926us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.410s	1.260ms	5	5	100.00
		aon_timer_csr_rw	1.340s	498.759us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	479.813us	5	5	100.00
		aon_timer_same_csr_outstanding	6.140s	2.714ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.410s	1.260ms	5	5	100.00
		aon_timer_csr_rw	1.340s	498.759us	20	20	100.00
		aon_timer_csr_aliasing	1.370s	479.813us	5	5	100.00
		aon_timer_same_csr_outstanding	6.140s	2.714ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	14.190s	8.568ms	5	5	100.00
		aon_timer_tl_intg_err	14.840s	8.573ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.840s	8.573ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.725m	209.429ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.89	99.33	93.67	100.00	--	98.40	99.51	48.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

2.aon_timer_stress_all_with_rand_reset.72498361269332122442831249586059115272149887129029140693089752380750659706004
Line 1069, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 72274333947 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 72274333947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.74156970844778991989251267142727934892545565430599661940082752637278467025262
Line 302, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1211926763 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1211926763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 4 failures.

10.aon_timer_stress_all.65861787273533548743738970188628109913023590167560194265411651162583133632575
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 448339078 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 448339078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.aon_timer_stress_all.8145027788974057342645520240599086581357551068073370360787975166792624120870
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 207975344709 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 207975344709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.