AON_TIMER Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	595.860us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	0.970s	1.018ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.430s	499.165us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.720s	13.001ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.560s	472.878us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	561.409us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.430s	499.165us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	472.878us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.180s	484.208us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	446.003us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.342m	55.324ms	50	50	100.00
V2	jump	aon_timer_jump	1.380s	532.466us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.536m	303.549ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.290s	514.194us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.740s	590.784us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.740s	590.784us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	0.970s	1.018ms	5	5	100.00
		aon_timer_csr_rw	1.430s	499.165us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	472.878us	5	5	100.00
		aon_timer_same_csr_outstanding	4.960s	2.151ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	0.970s	1.018ms	5	5	100.00
		aon_timer_csr_rw	1.430s	499.165us	20	20	100.00
		aon_timer_csr_aliasing	1.560s	472.878us	5	5	100.00
		aon_timer_same_csr_outstanding	4.960s	2.151ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	6.620s	4.062ms	5	5	100.00
		aon_timer_tl_intg_err	13.420s	8.278ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.420s	8.278ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.201m	263.063ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.99	99.33	93.67	100.00	--	98.40	99.51	49.04

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 5 failures.

9.aon_timer_stress_all_with_rand_reset.38746171858901452513602227004219613268418928235769338250798684954639353201691
Line 354, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14916600903 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14916600903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all_with_rand_reset.56338158897687257390205269016129483523402224801081049608425973746284362327377
Line 584, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 87353451620 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 87353451620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all has 1 failures.

13.aon_timer_stress_all.12832102977626185208811917227256725870883219896473677799968098586011234007329
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 41518673474 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 41518673474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---