AON_TIMER Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.500s	599.189us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.280s	1.205ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	433.523us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	32.460s	12.823ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.590s	528.757us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.570s	599.748us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	433.523us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	528.757us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.120s	487.146us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	513.760us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	56.650s	36.893ms	50	50	100.00
V2	jump	aon_timer_jump	1.500s	536.599us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.230m	603.001ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.290s	475.191us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.670s	482.106us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.670s	482.106us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.280s	1.205ms	5	5	100.00
		aon_timer_csr_rw	1.350s	433.523us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	528.757us	5	5	100.00
		aon_timer_same_csr_outstanding	5.380s	2.502ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.280s	1.205ms	5	5	100.00
		aon_timer_csr_rw	1.350s	433.523us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	528.757us	5	5	100.00
		aon_timer_same_csr_outstanding	5.380s	2.502ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	11.980s	7.724ms	5	5	100.00
		aon_timer_tl_intg_err	14.100s	8.239ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.100s	8.239ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	18.521m	689.828ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.45	99.33	93.67	100.00	--	98.40	99.51	51.82

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 4 failures.

10.aon_timer_stress_all_with_rand_reset.50102957887689388985282374876471745561214608890123470347263822393954099815085
Line 392, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36487254688 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 36487254688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.59184978143519649456998139677378620002714878983172942007948975495491716218032
Line 428, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28209058117 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 28209058117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all has 2 failures.

27.aon_timer_stress_all.33181148695870403804333604358093148935683611290063723768039920252663610259554
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 38232968565 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 38232968565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aon_timer_stress_all.49704446547979470722178723371572286102820214275534266877475636183100705201400
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 51000113393 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 51000113393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---