AON_TIMER Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: `5967df933a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	587.156us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.430s	1.180ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.370s	495.570us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	35.560s	13.100ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.590s	668.495us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.530s	547.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.370s	495.570us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	668.495us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.880s	312.030us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.010s	359.709us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.548m	59.537ms	50	50	100.00
V2	jump	aon_timer_jump	1.380s	574.446us	50	50	100.00
V2	stress_all	aon_timer_stress_all	7.250m	304.499ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.320s	511.826us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.670s	606.563us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.670s	606.563us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.430s	1.180ms	5	5	100.00
		aon_timer_csr_rw	1.370s	495.570us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	668.495us	5	5	100.00
		aon_timer_same_csr_outstanding	6.510s	2.198ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.430s	1.180ms	5	5	100.00
		aon_timer_csr_rw	1.370s	495.570us	20	20	100.00
		aon_timer_csr_aliasing	1.590s	668.495us	5	5	100.00
		aon_timer_same_csr_outstanding	6.510s	2.198ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	10.920s	7.808ms	5	5	100.00
		aon_timer_tl_intg_err	14.800s	8.828ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.800s	8.828ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.190m	101.867ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.60	99.33	93.67	100.00	--	98.40	99.51	46.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all_with_rand_reset has 4 failures.

15.aon_timer_stress_all_with_rand_reset.40160356709288270385457817791553285209008934087470998759893428899270478193344
Line 616, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28302393226 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 28302393226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all_with_rand_reset.109575558716107855262049983385457711893143357964386786947391797918024673641694
Line 638, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 54431740764 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 54431740764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all has 3 failures.

18.aon_timer_stress_all.74676175752640661689793294645602867346207027571818525569850806790359167863316
Line 261, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 769266136 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 769266136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.aon_timer_stress_all.24422165006825233867653808974126507461434116897510592253646020417397103197762
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 304499442746 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 304499442746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.