AON_TIMER Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.450s 568.489us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.100s 992.738us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.340s 487.435us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 25.590s 7.138ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.460s 705.044us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.490s 505.047us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.340s 487.435us 20 20 100.00
aon_timer_csr_aliasing 1.460s 705.044us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.060s 425.886us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 0.720s 510.782us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.343m 51.751ms 50 50 100.00
V2 jump aon_timer_jump 1.400s 532.826us 50 50 100.00
V2 stress_all aon_timer_stress_all 16.795m 636.032ms 47 50 94.00
V2 intr_test aon_timer_intr_test 1.450s 519.435us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.570s 2.185ms 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.570s 2.185ms 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.100s 992.738us 5 5 100.00
aon_timer_csr_rw 1.340s 487.435us 20 20 100.00
aon_timer_csr_aliasing 1.460s 705.044us 5 5 100.00
aon_timer_same_csr_outstanding 4.580s 2.957ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.100s 992.738us 5 5 100.00
aon_timer_csr_rw 1.340s 487.435us 20 20 100.00
aon_timer_csr_aliasing 1.460s 705.044us 5 5 100.00
aon_timer_same_csr_outstanding 4.580s 2.957ms 20 20 100.00
V2 TOTAL 237 240 98.75
V2S tl_intg_err aon_timer_sec_cm 6.440s 3.837ms 5 5 100.00
aon_timer_tl_intg_err 13.830s 8.571ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 13.830s 8.571ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 16.931m 362.797ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 422 430 98.14

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.04 99.33 93.67 100.00 -- 98.40 99.51 49.33

Failure Buckets

Past Results