AON_TIMER Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	558.691us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.030s	910.175us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	530.452us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.770s	13.684ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.420s	434.253us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.550s	561.762us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	530.452us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	434.253us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.170s	478.250us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.930s	305.241us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.305m	55.135ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	613.538us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.178m	589.472ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.310s	519.882us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.910s	517.142us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.910s	517.142us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.030s	910.175us	5	5	100.00
		aon_timer_csr_rw	1.330s	530.452us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	434.253us	5	5	100.00
		aon_timer_same_csr_outstanding	3.710s	1.715ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.030s	910.175us	5	5	100.00
		aon_timer_csr_rw	1.330s	530.452us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	434.253us	5	5	100.00
		aon_timer_same_csr_outstanding	3.710s	1.715ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	13.930s	8.285ms	5	5	100.00
		aon_timer_tl_intg_err	12.860s	8.129ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.860s	8.129ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.757m	93.484ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.03	99.33	93.67	100.00	--	98.40	99.51	49.30

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

13.aon_timer_stress_all_with_rand_reset.4930150218127595319117452456755228010547149173305942487007647364353084166564
Line 493, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 100712801702 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 100712801702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.aon_timer_stress_all_with_rand_reset.44459205159954347198174164351611126674864898105551173393801284902001279221628
Line 629, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 119450964738 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 119450964738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 2 failures.

33.aon_timer_stress_all.72564111478549078093009572827666757756440789822783619324215922835373790671386
Line 329, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 51118057217 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 51118057217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all.47418250074492231264810962791231416869041910631587888737154695728811439477358
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 6209296669 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6209296669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---