AON_TIMER Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	581.976us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	0.950s	1.137ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.340s	532.188us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	26.470s	11.688ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.660s	510.372us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.590s	626.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.340s	532.188us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	510.372us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.740s	329.469us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.200s	461.921us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.331m	51.893ms	50	50	100.00
V2	jump	aon_timer_jump	1.430s	554.458us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.473m	510.896ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	511.522us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.900s	1.122ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.900s	1.122ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	0.950s	1.137ms	5	5	100.00
		aon_timer_csr_rw	1.340s	532.188us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	510.372us	5	5	100.00
		aon_timer_same_csr_outstanding	6.450s	2.180ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	0.950s	1.137ms	5	5	100.00
		aon_timer_csr_rw	1.340s	532.188us	20	20	100.00
		aon_timer_csr_aliasing	1.660s	510.372us	5	5	100.00
		aon_timer_same_csr_outstanding	6.450s	2.180ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.140s	8.020ms	5	5	100.00
		aon_timer_tl_intg_err	12.140s	8.345ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.140s	8.345ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.019m	381.476ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.85	99.33	93.67	100.00	--	98.40	99.51	48.20

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

3.aon_timer_stress_all_with_rand_reset.102952461734584357612451265354976122204578043959424720760132512353532750133211
Line 596, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 121461838967 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 121461838967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aon_timer_stress_all_with_rand_reset.81116953229085750421364300560536218763210545446851393695008003653821964677353
Line 524, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17963127937 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 17963127937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 1 failures.

46.aon_timer_stress_all.64714508982026809708758680699018949806831187666828905888746843831438874012491
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/46.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 86611383632 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 86611383632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---